Typically, top and bottom sides of a semiconductor wafer are subjected to a plurality of stages of mirror-polishing. Specifically, the mirror-polishing is roughly divided into a rough polishing for enhancing the flatness of the semiconductor wafer, and a finish polishing for reducing the surface roughness of the semiconductor wafer.
Further, the mirror-polishing is not only applied to the top and bottom sides of the semiconductor wafer, but also to a chamfered portion of the semiconductor wafer in order to prevent a generation of dust from the chamfered portion.
The rough polishing is performed through a simultaneous double-sided polishing in which top and bottom sides of a semiconductor wafer received in a carrier are simultaneously polished. During the simultaneous double-sided polishing, the semiconductor wafer touches an inner circumferential surface of the carrier to cause scars and impressions on the chamfered portion. Accordingly, the mirror-polishing is applied to the chamfered portion after the rough polishing in order to remove the generated scars and impressions.
Typically, the chamfered portion is mirror-polished in two stages including: a first step for polishing the chamfered portion using an unwoven fabric polishing pad and abrasive-grain-containing polishing solution; and a second step for finishing the polishing using a suede polishing pad and abrasive-grain-containing polishing solution. The first step is performed in order to highly efficiently remove the scars and impressions caused on the chamfered portion. The second step is performed in order to flatten minute surface roughness of the chamfered portion.
However, since a soft polishing cloth is used as the polishing pad for mirror-polishing the chamfered portion, the soft polishing cloth is not only applied on the chamfered portion but also applied over the top and/or bottom side of the wafer during the progress of the polishing (sometimes referred to as an “over-polishing” hereinafter).
Specifically, an oxide film 101A present on a chamfered portion 101 of a semiconductor wafer 100 is removed in the first step as shown in FIG. 5A. However, as shown in FIG. 5B, not only the oxide film 101A present on the chamfered portion 101 but also an oxide film 102B present at a part of the oxide film 102A on a wafer surface 102, to which a polishing cloth (unwoven fabric) 111 of the polishing pad is applied, is removed. Further, a stress is locally concentrated to a border portion 103 between the wafer surface 102 and the chamfered portion 101 which emerges by removing the oxide film 102B, so that the polishing progresses around the border portion 103.
Next, subsequent to the first step, the oxide film 102B present at a part of the wafer surface 102, to which a polishing cloth (suede) 112 of the polishing pad is applied, is removed in the second step as shown in FIG. 5C. Then, a stress is locally applied to the border portion 103 between the exposed wafer surface 102 and the chamfered portion 101, so that the polishing further progresses around the border portion 103.
The above-described over-polishing reduces the thickness of the outer peripheral portion of the semiconductor wafer (sometimes referred to as an edge roll-off).
It has been disclosed that, in order to prevent the edge roll-off caused by the over-polishing, the polishing pad is formed by adhering at least two layers including a polishing cloth layer and a sponge layer whose hardness is lower than that of the polishing cloth layer, and the hardness of the polishing cloth layer is set at 40 or less in ASKER C hardness (see, for instance, Patent Literature 1). In Patent Literature 1, the width of the over-polishing can be reduced to 400 μm or less with the use of the above-structured polishing pad.
Another manufacturing method of a semiconductor wafer has been disclosed, in which a resin protection film is formed on top and bottom sides of a semiconductor wafer after a double-sided polishing, a mirror-finish chamfering step is performed, and subsequently the resin protection film is removed (see, for instance, Patent Literature 2). In Patent Literature 2, the resin protection film formed on the top and bottom sides of the semiconductor wafer restrains the over-polishing during the mirror-finish chamfering step to prevent the edge roll-off.